ANSI SP5.4.1:2017 pdf download.Latch-up Sensitivity Testing ofCMOS/BiCMOS Integrated Circuits-Transient Latch-up Testing Device Level.
This document defines procedures to characterize the latch-up sensitivity of integrated circuits triggered by fast transients.
1.3 Application
This document defines a characterization methodology which is intentionally kept as flexible as possible. This document does not define a qualification standard.
The characterization can be applied to:
• Test structures (for example, process assessment, component verification).
• Distinct pins of products (stand-alone and with “simple” external circuitries).
• I/O pins of systems and subsystems.
• Integrated circuits with or without external circuitry which is typical for the application or required for pre-conditioning the IC. The IC might be mounted on a printed-circuit board(PCB).
In order to perform the TLU test one has to define the pins under test and the testing parameters. This document is intended to be a guideline for the application engineer who defines the test and the test engineer who performs the test according to the definition and prepares a report.
The characterization is application specific. Hence, the focus of this document is on the general methodology and particularly on verification of the methodology.
TLU as defined in this document does not cover changes of functional states, even if those changes would result in a low-impedance path and increased power supply consumption.
2.0 REFERENCED DOCUMENTS
Unless otherwise specified, the latest issue, revision or amendment of the following documents form a part ofANSI SP5.4.1 to the extent specified herein:
ESD ADV1 .0, ESD Association Glossary of Terms
ANSI/ESD S20.20, Protection of Electrical and Electronic Parts, Assemblies and Equipment(Excluding Electrically Initiated Explosive Devices)
ANSI/ESD STM5.5.1, For Electrostatic Discharge Sensitivity Testing —Transmission Line Pulse(TLP) — Component Level2
IEC61 340-5-1, Electrostatics—Part 5-1: Protection of Electronic Devices from ElectrostaticPhenomena—General Requirements
JESD78E “IC Latch-up Test”, JEDEC, April 2O16
NOTE: For the use in this document, the version JESD78E is required.
JESD625, Requirements for Handling Electrostatic Discharge-Sensitive (ESDS) Devices4
3.0 DEFINITION OF TERMS
The following definitions are in addition to those found in ESD ADV 1.0, ESD Association’s Glossary of Terms:
functional state. The mode in which the device is operating.
NOTE: A device may have many different functional states each resulting in a different supply current. ground pin. The common or zero-potential pin(s) of the DUT.
NOTE: These pins are generally biased to 0 volts and all measurements are made relative to this reference. maximum operating voltage (maximum Value listed in the device data sheets for which the device will still meet all specifications under operating conditions. It is not the same as the absolute maximum voltage allowed without causing permanent damage.
maximum stress voltage (MSV). The maximum voltage allowed to be applied to the stressed pin during TLU testing without causing catastrophic damage to the device.
NOTE: MSV might depend on the TLU stress pulse width; it can be larger than the absolute maximum rated voltage.
nominal supply current (horn). The measured DC supply current for each VDD supply. The nominal supply current is in the range of supply currents possible under all normal operating states.
preconditioning. The process of setting the input states of a device and applying appropriate electrical signals until a particular desired functional state is achieved.
signal pins. Any connected pin that does not supply power or ground to the component.ANSI SP5.4.1 pdf download.